1. Field of Invention
This invention relates generally to silicon-on-insulator (SOI) CMOS devices and specifically to processes for forming SOI devices having a low resistance.
2. Description of Related Art
Silicon-on-insulator (SOI) devices are those which are formed in a thin silicon layer which overlies an insulating layer. The insulating layer, in turn, overlies a second silicon layer. Fabricating integrated circuit (IC) devices in a thin silicon-on-insulator (SOI) layer, as opposed to fabricating such devices in a much thicker bulk silicon structure, allows for lower parasitic capacitances and for greater channel currents which, in turn, allows for faster speeds. The lower parasitic capacitances also allow for reduced substrate crosstalk and, thus, for reduced noise. In order to fully realize these advantages, the SOI layer within which IC devices are fabricated should be less than approximately 1000 .ANG. so that the source and drain regions of these IC devices are proximate to the underlying insulating layer. Further, the source and drain regions of devices formed within an SOI layer should be shallow in order to minimize short channel effects.
Unfortunately, semiconductor devices fabricated in a thin SOI layer and having relatively shallow source and drain regions typically exhibit an unacceptably high series resistance between the source and drain regions. This high series resistance results in slower speeds and therefore may abrogate the superior speeds when using SOI technologies. In order to decrease the series resistance of such semiconductor devices, a layer of silicide is typically formed within the source and drain. The silicide material may be, for instance, Titanium Silicide (TiSi.sub.2) or Cobalt Silicide (CoSi.sub.2).
For instance, a layer of titanium silicide is formed within the source and drain of a transistor by first depositing a thin film of titanium over the surface of the transistor. The transistor is then thermally annealed in a nitrogen ambient at a temperature between approximately 400-700 degrees Celsius for approximately 10-200 seconds to induce reactions between titanium and silicon. Thus, titanium from within the deposited titanium layer and silicon from within the source and drain react to form a titanium silicide (TiSi.sub.x) layer substantially within the source and drain. Since titanium does not significantly react with insulating materials such as, for instance, oxides and nitrides, portions of the titanium layer overlying sidewall spacers and field oxide regions remain in a metallic titanium state. These thermally induced reactions also produce a layer of titanium nitride over the transistor. The titanium nitride layer and un-reacted portions of the deposited titanium layer are removed during a subsequent etching step. The titanium silicide layer lying substantially within the source and drain of the transistor, which is left intact, increases the conductivity of the source and drain and, therefore, reduces the series resistance of the transistor. A second thermal annealing step converts the titanium silicide into a substantially stoichiometric composition. For instance, where the titanium silicide is in the form TiSi.sub.2, the second annealing converts the TiSi.sub.2 from a C.sub.49 phase to a more conductive C.sub.54 phase, thereby further reducing the series resistance of the transistor.
Forming a layer of silicide in the manner described above is, however, problematic if the semiconductor device is fabricated within a thin silicon layer, such as an SOI layer, which has a thickness of less than approximately 1000 .ANG.. These thin silicon layers cannot source enough silicon during thermally induced reactions with titanium and, as a result, an undesirable amount of titanium agglomeration occurs within the resultant titanium silicide layer. The agglomeration of titanium decreases the conductivity of the silicide layer which, as discussed above, produces an undesirable increase in the series resistance of a transistor. The agglomeration of titanium may also degrade the performance and reliability of the transistor.
Increasing the thickness of the underlying silicon layer has been found to reduce the agglomeration of titanium during formation of titanium silicide. However, since increasing the thickness of the silicon layer undesirably increases parasitic capacitances therein, such an approach undesirably involves a difficult trade-off between maximizing the conductivity of the silicide layer and minimizing parasitic capacitances within the silicon layer. In response thereto, another approach has been proposed in which conventional methods of forming an elevated source and drain are applied to the fabrication of semiconductor devices formed in thin silicon layers such as, for instance, an SOI layer. The junction depths of the resultant elevated source and drain are increased, while preserving the thickness portions of the silicon layer lying between the elevated source and drain, i.e., the channel region. The deeper source and drain reduce the agglomeration of titanium during formation of titanium silicide layers therein. Since the thickness of other portions of the silicon layer are not increased, parasitic capacitances within the silicon layer are not significantly increased.
In this approach, a layer of gate oxide is first grown over an SOI layer. A layer of polysilicon is then deposited and patterned to form a control gate of the transistor. After sidewall spacers are formed in a well known manner, portions of the gate oxide overlying portions of the SOI layer where the source and drain will be formed are removed, thereby exposing these portions of the SOI layer. Next, an epitaxial layer of silicon is selectively grown over these exposed portions of the SOI layer and then doped using, for instance, ion implantation, to a desired dopant concentration. The resultant source and drain are formed substantially within the epitaxial layer and, thus, are "elevated" with respect to the gate. The elevated source and drain are then silicided, as described above, to reduce the series resistance of the transistor. Since the elevated source and drain lie substantially above the original SOI layer, a greater amount of silicon is available during formation of the silicide layer within the elevated source and drain. As a result, the titanium agglomerates to a much lesser extent, thereby increasing the conductivity of the silicide layer and, thus, further decreasing the series resistance of the transistor.
Unfortunately, such a method of forming an elevated source and drain of a transistor which is fabricated on a thin SOI layer is not only expensive but also is very difficult to control. Specifically, the thickness and quality of the epitaxial layer grown over portions of the SOI layer tend to vary between wafer runs, thereby undesirably resulting in device specification inconsistencies and reliability problems.
In another approach for forming elevated source and drain regions of a transistor, such as that disclosed in U.S. Pat. No. 5,434,093, issued on Jul. 18, 1995 to Chau et al, a dielectric layer is first formed over the substrate. A portion of the dielectric layer is removed using a suitable etchant, thereby forming a trench within the dielectric layer. After a polysilicon gate and associated sidewall spacers are formed within the trench, the dielectric layer is removed, thereby exposing portions of the underlying silicon substrate. Source and drain regions are formed within these exposed portions of the substrate. Since the trench may be etched into the substrate, the source and drain regions are elevated with respect to the gate.
The disadvantage of techniques such as that disclosed in the Chau et al patent is that the channel length of devices formed in accordance thereof is determined by the photo-lithographic and etching process used. Thus, the precision with which channel length may be controlled is limited by alignment tolerances and minimum dimensions of photo-lithography and etching techniques.